1. Field of the Invention
The present invention generally relates to a semiconductor structure with a slimmed spacer and the method for making the semiconductor structure with the slimmed spacer. In particular, the present invention is directed to a semiconductor structure with a slimmed spacer and the method for making the semiconductor structure with the slimmed spacer.
2. Description of the Prior Art
With the trend of miniaturization of semiconductor device dimensions, for example for the semiconductor processes with the critical dimensionless than 65 nm, the scale of the gate, the source and the drain of a transistor decreases in accordance with the decrease in critical dimension (CD). Due to the intrinsic physical limitation of the materials which are used, the decrease in the scale of the gate, the source and the drain in a transistor, such as a PMOS or an NMOS, results in the decrease of carriers that determine the magnitude of the current in the transistor element, and this can therefore adversely affect the performance of the transistor. As a result, increasing carrier mobility in order to boost up a MOS transistor is an important topic in the field of current semiconductor techniques.
In various current techniques, it is possible to generate a mechanical stress on purpose in the channel to increase the carrier mobility. For example, a silicon germanium (SiGe) channel layer is epitaxically formed on the Si substrate to construct a compressive strained channel to substantially increase the hole mobility. Or alternatively, a silicon channel is epitaxically formed on the germanium (SiGe) layer to construct a tensile strained channel to substantially increase the electron mobility.
In addition, among the current techniques, one of the most popular and well-known methods is to form a corresponding stress therein when a shallow trench isolation, a source, a drain, or a contact etch stop layer (CESL) is formed. For example, the contact etch stop layer (CESL) with a stress turns into a stress layer to provide a gate channel with a compression stress or a tensile stress in order to modify the carrier mobility. For instance, a compression stress is constructed in order to modify the carrier mobility. Generally speaking, the greater the stress is, the higher gain for the carrier mobility is. Accordingly, persons of ordinary skills in the art all endeavor themselves in developing a processing method to pursue a greater stress gain. However, with the trend of miniaturization of semiconductor device dimensions, the stress which is created by the above-mentioned techniques seems to be not enough any more.
Furthermore, during the manufacturing process of semiconductors, a pair of protective and self-aligning spacers is formed to surround the elements of the semiconductor devices, such as the gates. However, when the spacers are formed, some undesirable side effects sometimes occur.
For example, due to the shrinkage of the critical dimension and the increasing integration of elements, the pitch between elements becomes too small to maintain a proper space to accommodate the stress so that the stress layer on the spacers of the adjacent elements merge and the stress in the stress layer cannot be properly delivered to the gate channel. Once the expected tensile or the compressive stress fails, the performance of the elements may deteriorate or fail, too.
Therefore, a novel semiconductor structure and a method for making such semiconductor structure are still needed to create a new way to properly and effective pass the stress in the stress layer to the underlying gate channel as much as possible.